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• W2950196727 abstract "The trend in industry is towards heterogeneous multicore processors (HMCs), including chips with CPUs and massively-threaded throughput-oriented processors (MTTOPs) such as GPUs. Although current homogeneous chips tightly couple the cores with cache-coherent shared virtual memory (CCSVM), this is not the communication paradigm used by any current HMC. In this paper, we present a CCSVM design for a CPU/MTTOP chip, as well as an extension of the pthreads programming model, called xthreads, for programming this HMC. Our goal is to evaluate the potential performance benefits of tightly coupling heterogeneous cores with CCSVM." @default.
• W2950196727 created "2019-06-27" @default.
• W2950196727 creator A5005628986 @default.
• W2950196727 creator A5072847774 @default.
• W2950196727 date "2013-10-29" @default.
• W2950196727 modified "2023-09-27" @default.
• W2950196727 title "Evaluating Cache Coherent Shared Virtual Memory for Heterogeneous Multicore Chips" @default.
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• W2950196727 hasPublicationYear "2013" @default.
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