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- W2952202580 abstract "In order to improve the performance of the digital lock-in amplifier and reduce the logic resources occupied in hardware, this paper designs a modular design scheme based on DSP Builder, making the design of the digital lock-in amplifier intuitive and simplified. This paper designs an internal excitation mode digital lock-in amplifier. After the simulation, the compiled program is downloaded to the FPGA device. The logic elements consumption rate is only 18%, reducing the resource usage of FPGA devices effectively. Experimental results show that the signal measurement error is less than 0.05% when the SNR of the measured signal is -14dB and the amplitude is greater than 500mV. Therefore, the digital lock-in amplifier can effectively detect weak signals." @default.
- W2952202580 created "2019-06-27" @default.
- W2952202580 creator A5016341553 @default.
- W2952202580 creator A5059554395 @default.
- W2952202580 date "2018-12-01" @default.
- W2952202580 modified "2023-09-30" @default.
- W2952202580 title "Design of Digital Lock-in Amplifier Based on DSP Builder" @default.
- W2952202580 cites W2156704184 @default.
- W2952202580 cites W2358272063 @default.
- W2952202580 cites W72901485 @default.
- W2952202580 doi "https://doi.org/10.1109/itoec.2018.8740454" @default.
- W2952202580 hasPublicationYear "2018" @default.
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