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- W2954786284 abstract "The improved architecture of IFFT is developed and presented in this paper. Number of arithmetic operation is more in the normal working of conventional Inverse Fast Fourier Transform. An enhanced pruning algorithm is utilized to reduce the number of arithmetic operations in the IFFT architecture. The performance of the improved IFFT architecture is estimated to find its suitability for the low power Wireless communication system. It is implemented in 8-point IFFT architecture using decimation in frequency algorithm using hardware description language. It is implemented in XC7z020clg484-1 from Zynq-7000 family with a frequency of 220 MHz. It is found that the improved IFFT architecture reduces maximum of 40% of the arithmetic operations, which reduces the power consumption by maximum of 10%. Hence the improved IFFT architecture can be used in the signal processing units in wireless application." @default.
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- W2954786284 date "2019-11-01" @default.
- W2954786284 modified "2023-09-25" @default.
- W2954786284 title "FPGA implementation of IFFT architecture with enhanced pruning algorithm for low power application" @default.
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- W2954786284 doi "https://doi.org/10.1016/j.micpro.2019.06.010" @default.
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