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- W2955259612 abstract "During the top-down design process, it is essential to be able to accurately and efficiently determine the physical and timing characteristics of a design. This translates to a need for an accurate area and performance estimator that can evaluate the various design tradeoffs available during synthesis. Existing area and performance estimators used in synthesis do not provide accurate and efficient measures to enable the synthesis process to converge towards the optimal solution. This dissertation proposes area and performance estimators which are based on predictive models of the layout. This work considers the impact of physical design process such as wiring and floorplanning while evaluating the area and timing characteristics. The predictive models are an order of magnitude faster than the physical design process and typically run to completion in a few seconds. At the same time they are able to provide accurate estimates of the characteristics of the layout. The estimators can be used at both RT level and gate level of abstractions. The estimators also provide additional features such as the information about the critical path list and the estimated floorplan. They can be used to assess whether the synthesized design would satisfy design constraints after the physical design is performed. With this information, a decision to re-synthesize the design can be undertaken prior to performing physical design. Thus estimation driven synthesis could help prune the top-down design cycle time significantly, making high level synthesis a viable option for use in commercial products." @default.
- W2955259612 created "2019-07-12" @default.
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- W2955259612 date "1994-01-02" @default.
- W2955259612 modified "2023-09-27" @default.
- W2955259612 title "Area and timing estimation techniques for top-down VLSI chip design" @default.
- W2955259612 hasPublicationYear "1994" @default.
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