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- W2955479216 abstract "This article presents a low power consumption, high speed multiplier, based on a lowest transistor count novel structure when compared with other traditional multipliers. The proposed structure utilizes 4×4-bit adder units, since it is the base structure of digital multipliers. The main merits of this multiplier design are that: it has the least adder unit count; ultra-low power consumption and the fastest propagation delay in comparison with other gate implementations. The figures demonstrate that the proposed structure consumes 32% less power than using the bypassing Ripple Carry Array (RCA) implementation. Moreover, its propagation delay and adder units count are respectively about 31% and 8.5% lower than the implementation using the bypassing RCA multiplier. All of these simulations were carried out using the HSPICE circuit simulation software in 0.18 μm technology at 1.8 V supply voltage. The proposed design is thus highly suitable in low power drain and high-speed arithmetic electronic circuit applications." @default.
- W2955479216 created "2019-07-12" @default.
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- W2955479216 date "2019-07-01" @default.
- W2955479216 modified "2023-09-24" @default.
- W2955479216 title "The Cascade Carry Array Multiplier – A Novel Structure of Digital Unsigned Multipliers for Low-Power Consumption and Ultra-Fast Applications" @default.
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- W2955479216 doi "https://doi.org/10.33166/aetic.2019.03.003" @default.
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