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• W2959662934 abstract "The design methodology based on standard cells is widely used in a broad range of very-large-scale integration (VLSI) applications. Furthermore, several optimization algorithms can be employed to address different constraints such as power consumption or reliability. This paper evaluates the implications of the usage of complex logic cells from a 45-nm standard-cell library to the single-event transient (SET) sensitivity under heavy ions. Results show that even though a reduction in the layout area is obtained when adopting complex logic gates, a slight reduction in the total sensitive area of the circuit is observed. Moreover, the effectiveness of the logical masking can be suppressed, leading to a higher SET cross section for high particle linear energy transfer (LET)." @default.
• W2959662934 created "2019-07-23" @default.
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• W2959662934 date "2019-07-01" @default.
• W2959662934 modified "2023-10-18" @default.
• W2959662934 title "Impact of Complex Logic Cell Layout on the Single-Event Transient Sensitivity" @default.
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• W2959662934 doi "https://doi.org/10.1109/tns.2019.2918077" @default.
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