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• W2960670153 abstract "A critical technological challenge over the past few decades has been to achieve low-power operation without sacrificing performance. This led to the development of computing units that can normally be turned off when not in use and turned on instantly with full performance, when required thereby helping in eliminating leakage power. However, with direct power-down, the states in local memories (SRAM) and volatile registers (SRAM-based flip-flop) will be lost. Thus, to have a power-down mode in SRAM-based memories and Flip-Flops (FFs), the data states are off-loaded to an external nonvolatile storage array, thus giving rise to NV-SRAM/NV-FF circuits (i.e. nonvolatile SRAM/nonvolatile Flip-flop). In this chapter, we present a real-time 4T-2R NV-SRAM bitcell using HfO(_x) based OxRAM (oxide based random access memory) devices. We will discuss the working principle, programming methodologies and the stability of NV-SRAM bitcell. We will further present a novel NV-FF design based on 4T-2R NV-SRAM bitcell and will provide an insight into its working and operating modes." @default.
• W2960670153 created "2019-07-23" @default.
• W2960670153 creator A5008011360 @default.
• W2960670153 creator A5062738035 @default.
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• W2960670153 date "2019-07-17" @default.
• W2960670153 modified "2023-09-23" @default.
• W2960670153 title "CMOS-OxRAM Based Hybrid Nonvolatile SRAM and Flip-Flop: Circuit Implementations" @default.
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• W2960670153 doi "https://doi.org/10.1007/978-981-13-8379-3_2" @default.
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