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- W2963663066 abstract "Circuit designing of variable delay elements has been in practice for decades. However, these delay circuits have not been able to demonstrate equal rise and fall delays at its output. One of the major reasons for this failure is that the construction of delay circuits is non-symmetric. In this paper, we have attempted in designing a simple symmetric architecture which can produce the delayed output with almost identical rise and fall time. The proposed delay circuit is simulated using 90 nm GPDK in Cadence Virtuoso® initially for an input signal of 1 GHz at power supply Vdd = 1.1 V, and the results infer that the contrast (Δ) in rise and fall time is very small even during the input variations." @default.
- W2963663066 created "2019-07-30" @default.
- W2963663066 creator A5009067589 @default.
- W2963663066 creator A5051418913 @default.
- W2963663066 date "2019-07-26" @default.
- W2963663066 modified "2023-09-26" @default.
- W2963663066 title "A Variable Delay Circuit to Develop Identical Rise/Fall Time in the Output" @default.
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- W2963663066 doi "https://doi.org/10.1007/978-981-13-8687-9_28" @default.
- W2963663066 hasPublicationYear "2019" @default.
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