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- W2963810130 abstract "300 μm thick 3C-SiC epilayer was grown on off-axis 4H-SiC(0001) substrate with a high growth rate of 1 mm/hour. Dry oxidation, wet oxidation and N 2 O anneal were applied to fabricate lateral MOS capacitors on these 3C-SiC layers. MOS interface obtained by N 2 O anneal has the lowest interface trap density of 3~4x10 11 eV -1 cm -2 . Although all MOS capacitors still have positive net charges at the MOS interface, the wet oxidised sample has the lowest effective charge density of ~9.17x10 11 cm -2 ." @default.
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- W2963810130 date "2019-07-01" @default.
- W2963810130 modified "2023-10-07" @default.
- W2963810130 title "Electrical Characterisation of Thick 3C-SiC Layers Grown on Off-Axis 4H-SiC Substrates" @default.
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- W2963810130 doi "https://doi.org/10.4028/www.scientific.net/msf.963.353" @default.
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