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- W2964674759 abstract "The main challenge in designing a loop filter for a phase locked loop (PLL) is the physical dimensions of the passive elements used in the circuit that occupy large silicon area. In this paper, the basic features of a charge-controlled memristor are studied and the design procedures for various components of a PLL are examined. Following this, we propose a memristor-based filter design which has its resistance being replaced by a memristor in order to reduce the die area and achieve a low power consumption. We obtained a tuning range of 741–994 MHz, a stable output frequency of 1 GHz from the transfer characteristics of voltage-controlled oscillator (VCO), and an improved settling time. In addition to reduced power consumption and area occupied on the chip, our design shows a high reliability over wider range of temperature variations." @default.
- W2964674759 created "2019-08-13" @default.
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- W2964674759 date "2019-07-29" @default.
- W2964674759 modified "2023-10-02" @default.
- W2964674759 title "Memristor-Based Loop Filter Design for Phase Locked Loop" @default.
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- W2964674759 doi "https://doi.org/10.3390/jlpea9030024" @default.
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