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- W2965677982 abstract "An ADC-based receiver is demonstrated for NRZ/PAM4 modulation, featuring a TDC-assisted multi-bit/cycle asynchronous SAR ADC with embedded IIR equalization filter. It re-uses the existing sampling network of time-interleaved ADCs and incorporates active Gm-C integrators to form a tunable IIR equalizer response. The prototype is fabricated in 65 nm CMOS and achieves an efficiency of 2.43 pJ/b using 12.8-Gbuad PAM4. The 8-way time-interleaved ADC measures 4.84 peak effective-number-of-bit with power consumption of 36.3 mW." @default.
- W2965677982 created "2019-08-13" @default.
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- W2965677982 date "2019-04-01" @default.
- W2965677982 modified "2023-09-26" @default.
- W2965677982 title "A 12.8-Gbaud ADC-based NRZ/PAM4 Receiver with Embedded Tunable IIR Equalization Filter Achieving 2.43-pJ/b in 65nm CMOS" @default.
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- W2965677982 doi "https://doi.org/10.1109/cicc.2019.8780118" @default.
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