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• W2965877424 abstract "This paper presents a frequency-aware CMOS active rectifier with dual-loop adaptive delay compensation for capacitively powered biomedical implants with high power budgets. To support operation under a wide range of input frequencies, output power levels, and load values, dual-loop adaptive delay compensation is used to concurrently provide high resolution and high dynamic range in switched-offset currents of comparators that can be automatically reconfigured for low- and high-speed operation modes for adaptation to the input frequency. Fabricated in $0.18 mu mathrm { m }$ 1P/6M CMOS, the rectifier features power conversion efficiency (PCE) of $gt84.4$% (peak of 91.5%) and voltage conversion ratio (VCR) of $gt88.6$% (peak of 95.1%), when operating in 1–10MHz and driving a load of $300 Omega$. Moreover, for a load range of $20 Omega-1 mathrm{k} Omega$ at 5MHz, PCE of 81– 91.8% and VCR of 78.4–95.4% are achieved, with maximum output power of $sim$232 mW at 50$omega$ with PCE of 90.1%." @default.
• W2965877424 created "2019-08-13" @default.
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• W2965877424 date "2019-04-01" @default.
• W2965877424 modified "2023-09-26" @default.
• W2965877424 title "A 1–10MHz Frequency-Aware CMOS Active Rectifier with Dual-Loop Adaptive Delay Compensation and >230 mW Output Power for Capacitively Powered Biomedical Implants" @default.
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• W2965877424 doi "https://doi.org/10.1109/cicc.2019.8780243" @default.
• W2965877424 hasPublicationYear "2019" @default.
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