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- W2967405644 abstract "This paper presents a 71 GHz fully on-chip 3-stage inductor-peaked rectifier in 65-nm CMOS technology. The multistage rectifier is the bottleneck in realizing on-chip wireless power receivers. In this paper, sensitivity and efficiency problems of the mm-wave rectifier are discussed and a 3-stage inductor-peaked rectifier structure is proposed and realized. By cascading inductor-peaked rectifiers with optimized layout, the measured rectifier provide 1 V output voltage with 5 dBm input power at 71 GHz, it also reaches 8% efficiency with 720 µA current load. Compared to previous work of 45 GHz rectifier with 1.2% efficiency [1] and 62 GHz with 7% efficiency [2], this work provides higher efficiency and higher output voltage for mm-wave wireless power receivers." @default.
- W2967405644 created "2019-08-22" @default.
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- W2967405644 date "2019-05-01" @default.
- W2967405644 modified "2023-09-26" @default.
- W2967405644 title "A 71 GHz 3-Stage Rectifier with 8% Efficiency" @default.
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- W2967405644 doi "https://doi.org/10.1109/ieee-iws.2019.8804129" @default.
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