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• W2967927424 abstract "Two-dimensional time-division-multiplexing (2DTDM) was recently proposed to minimize both the time for testing 3D Systems-on-Chips (SoCs) and the number of through-siliconvias (TSVs). Even though 2D-TDM exploits the short vertical interconnections to transfer very fast the test-data to the various layers of the stack, the bus-based test-access-mechanism (TAM) at each layer imposes excessive routing overhead and long intra-die delays that compromise the test-time benefits, especially when the stack layers are unbalanced in terms of test-times. In this paper, we propose a new TDM-based TAM architecture for 3D SoCs, which supports non-regular division of the frequency among the various layers of the stack using very short daisy-chain intra-die connections. The proposed 3D TAM architecture is optimized by the means of the K3 design-automation process that combines the Kruskal algorithm, the Complete Karmarkar-Karp heuristic and a new optimization heuristic proposed in this paper. Experiments performed on a 3D benchmark integrated circuit (IC) show that significant test-time and routing savings are achieved." @default.
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• W2967927424 date "2019-05-01" @default.
• W2967927424 modified "2023-09-27" @default.
• W2967927424 title "K3 TAM Optimization for Testing 3D-SoCs using Non-Regular Time-Division-Multiplexing" @default.
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• W2967927424 doi "https://doi.org/10.1109/ets.2019.8791520" @default.
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