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• W2969424124 abstract "For the first time, we propose a 3D-monolithic SRAM architecture with a local back-plane for top-tier transistors enabling local back-bias assist techniques without area penalty as well as the capability to route two additional row-wise signals on individual back-planes. Experimental data are extracted from a 14nm planar Fully-Depleted-Silicon-on-Insulator (FDSOI) <tex xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>$0.078mu mathrm{m}^{2}$</tex> SRAM in order to properly model 3D top-tier cells. Simulations show this technique yields a 7% bitline capacitance reduction, a 12%/16% read/write access time improvement at <tex xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>$V_{DD}=0.8mathrm{V}$</tex> and a reduction of minimum operating voltage <tex xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>$V_{min}$</tex> by 60mV at <tex xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>$6sigma$</tex> w.r.t. planar SRAMs." @default.
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• W2969424124 date "2019-04-01" @default.
• W2969424124 modified "2023-09-26" @default.
• W2969424124 title "Novel Fine-Grain Back-Bias Assist Techniques for 14nm FDSOI Top-Tier SRAMs integrated in 3D-Monolithic" @default.
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• W2969424124 doi "https://doi.org/10.1109/vlsi-tsa.2019.8804649" @default.
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