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- W2972920497 abstract "This paper presents a voltage-controlled multistage gate driver topology for delay time minimization that improves the converter output voltage quality while supplying a motor load. Three gate driver topologies for SiC MOSFETs are compared based on their dead time requirement in a bridge leg converter. Experimental results of the gate driver delay times are reported and are used as input to a simulated motor drive application. Results show that turn-off delay times can be reduced by up to 74 % for the multistage driver compared to the conventional counterpart when the rate of change for the converter voltage output is limited to 10 V/ns. Furthermore, minimizing the dead time increases the linearity region of the output voltage from the converter by 1.8 % to 3.8 % and reduces the current THD in the linear region by up to 7.7 % when switching at 15kHz." @default.
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- W2972920497 date "2019-05-01" @default.
- W2972920497 modified "2023-09-24" @default.
- W2972920497 title "Minimization of dead time effect on bridge converter output voltage quality by use of advanced gate drivers" @default.
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- W2972920497 doi "https://doi.org/10.23919/icpe2019-ecceasia42246.2019.8797077" @default.
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