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• W2973406619 abstract "The generation of power-clocks in adiabatic integrated circuits is investigated. Specifically, we consider the energy efficiency of a 2-step charging strategy based on a single tank-capacitor circuit. We have investigated the impact of various parameters such as tank-capacitance to load capacitance ratio, ramping time, transistors sizing and power supply voltage scaling on energy recovery achievable in the 2-step charging circuit. We show that energy recovery achievable in the 2-step charging circuit depends on the tank-capacitor and load capacitor size concluding that tank-capacitance (CT) versus load capacitance (CL) is the significant parameter. We also show that the energy performance depends on the ramping time and improves for higher ramping times (lower frequencies). Energy recovery also improves if the transistors sizes in the step charging circuit are sized at their minimum dimensions. Lastly, we show that energy recovery decreases as the power supply voltage is scaled down. Specifically, the decrease in the energy recovery with decreasing power supply is significant for lower ramping times (higher frequencies). We propose that a Ct/Cl ratio of 10, keeping the width of the transistors in the step charging circuit minimum, can be chosen as a convenient ‘rule-of-thumb’ in practical designs." @default.
• W2973406619 created "2019-09-26" @default.
• W2973406619 creator A5004452484 @default.
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• W2973406619 date "2016-09-01" @default.
• W2973406619 modified "2023-09-23" @default.
• W2973406619 title "Energy efficiency of 2-step charging power-clock for adiabatic logic" @default.
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• W2973406619 doi "https://doi.org/10.1109/patmos.2016.7833684" @default.
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