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- W2976771476 abstract "This brief presents a high efficiency fully integrated high-voltage (HV) pulse driver in standard CMOS. Powered by a standard I/O DC voltage of 2.5 V, the proposed system employs an optimized 4-stage cross-coupled switched-capacitor voltage multiplier (SCVM) together with an on-chip HV output driver to generate HV pulses of >10 V. We propose an area-efficient HV output driver stage to reach up to 12% total active area reduction when compared with the conventional implementation while maintaining the low static power characteristics. We also present a synchronous charge compensation (SQC) technique to alleviate the loading-dependent signal distortion through reducing the HV rail voltage droop and improving the HV pulse settling time during the driver output transitions. Fabricated in 65-nm bulk CMOS, the chip prototype can successfully generate HV pulses from 250 kHz to 1 MHz with a 15 pF load while ensuring no device breakdown. Measurement results demonstrate a peak SCVM power conversion efficiency (PCE) of 50% and an overall driving efficiency of 12.25%. The chip prototype attains a $sim 2times $ faster output pulse transition speed compared with the state-of-the-art." @default.
- W2976771476 created "2019-10-03" @default.
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- W2976771476 date "2019-10-01" @default.
- W2976771476 modified "2023-09-24" @default.
- W2976771476 title "Fully Integrated High Voltage Pulse Driver Using Switched-Capacitor Voltage Multiplier and Synchronous Charge Compensation in 65-nm CMOS" @default.
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- W2976771476 doi "https://doi.org/10.1109/tcsii.2019.2921653" @default.
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