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• W2979663376 abstract "Over the past several decades, the performance of existing complementary metal oxide semiconductor (CMOS) technology has been improved by scaling of the CMOS transistors size. However, the performance of nanometre scale CMOS-based designs is limited due to the short-channel effect and process variation. The single electron transistor (SET) is a promising advanced nanometre scale device that can mitigate these grave issues. In this study, a novel SET-based computing system is designed and simulated at a supply voltage of 0.8 V, so that it can be 3D integrated with existing CMOS technology. The SET design parameters are considered based on SET fabricated by nanodamascene process for room temperature operation. The computing system works at frequency of 5 GHz with 2.522 μW power dissipation considering interconnect parasites. The frequency and power dissipation of the SET-based design is nearly 5 times better and 1.6 times lower than for the same design using 16 nm CMOS technology. The results and various analyses show that the SET-based systems are highly efficient and hence very effective to incorporate in next-generation very large scale integration designs. The SET-based design can be also 3D stacked in tandem with existing CMOS technology to achieve higher benefits in terms of speed, power, density, footprint, and functionality." @default.
• W2979663376 created "2019-10-18" @default.
• W2979663376 creator A5000010949 @default.
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• W2979663376 date "2020-02-12" @default.
• W2979663376 modified "2023-10-16" @default.
• W2979663376 title "Design of prominent SET‐based high performance computing system" @default.
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• W2979663376 doi "https://doi.org/10.1049/iet-cds.2019.0166" @default.
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