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- W2984019013 abstract "This paper presents a novel frequency tripler circuit topology which yields a remarkable improvement on the suppression of the driving signal frequency at the output, compared to conventional designs exploiting transistors in class-C. The active core of the circuit approximates the transfer characteristic of a third-order polynomial that ideally produces only a third-harmonic of the input signal. Implemented in a 55nm SiGe-BiCMOS technology and consuming 13.6mA from 1.7V, the tripler demonstrates ~40dB suppression of the input signal and its 5th harmonic over 16% factional bandwidth and robustness to power variation of the driving signal over a 15dB range." @default.
- W2984019013 created "2019-11-22" @default.
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- W2984019013 date "2019-09-01" @default.
- W2984019013 modified "2023-09-26" @default.
- W2984019013 title "40GHz Frequency Tripler with High Fundamental and Harmonics Rejection in 55nm SiGe-BiCMOS" @default.
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- W2984019013 doi "https://doi.org/10.1109/esscirc.2019.8902920" @default.
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