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- W2986345979 abstract "Ever increasing needs of data rate in Modern Wireless Communication Standards gives design challenges for efficient hardware realization of channel coding schemes. In this article, turbo channel coding scheme is presented and an optimized Turbo Decoder is proposed using VLSI optimization techniques in its hardware realization. To optimize the Turbo decoder, in terms of performance parameters such as throughput, latency, silicon area and power consumption than conventional designs, this design is proposed with Single SISO decoder instead of two SISO decoders and Re-Configurable (block lengths of 40 to 6144) Recursive Computational QPP interleaver /de-interleaver in its structure. To reduce the computational latency, parallel computation of state metrics and branch metrics is proposed. Also, intelligent memory scheduling is introduced in the proposed design to lower the memory necessity. In the proposed Turbo decoder, Max-log-MAP iterative decoding algorithm and contention free QPP interleaver has been adopted. The proposed optimized Max-Log-Map Turbo decoder implemented with 28nm CMOS technology and could be used for higher degree of parallelism to achieve higher throughput of decoding." @default.
- W2986345979 created "2019-11-22" @default.
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- W2986345979 date "2019-03-01" @default.
- W2986345979 modified "2023-09-25" @default.
- W2986345979 title "Performance improvement of Turbo Decoder using VLSI Optimization Techniques" @default.
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- W2986345979 doi "https://doi.org/10.1109/vitecon.2019.8899585" @default.
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