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• W2989594867 abstract "This article presents a single-phase symmetrical and asymmetrical multilevel inverter (MLI) topology. The presented topology can generate 9-level output voltage in a symmetrical configuration and 13- and 17-level output voltage in asymmetrical configuration with a single cell. The number of output levels can be improved further by increasing either the number of cells or switches in a single cell. The presented topology contains the least number of dc sources, semiconductor switches, capacitors, and diodes compared with classical and recently proposed topologies. Reduction in component count decreases the size, complexity, and cost of the overall converter. A detailed comparison has been done of the presented topology with the recently proposed topologies in terms of dc sources, semiconductor switches, capacitor, and total blocking voltage. Finally, to validate the presented concept, the prototype of the presented 9-, 13-, and 17-level MLI topologies has been tested in the laboratory for different switching frequencies, different modulation indexes, sudden load changes, and nonlinear load." @default.
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• W2989594867 date "2021-02-01" @default.
• W2989594867 modified "2023-09-30" @default.
• W2989594867 title "Symmetrical and Asymmetrical Reduced Device Multilevel Inverter Topology" @default.
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• W2989594867 doi "https://doi.org/10.1109/jestpe.2019.2955279" @default.
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