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- W2989763669 abstract "A digital low-dropout (DLDO) regulator using p-type MOS (PMOS) and n-type MOS (NMOS) switches is proposed to achieve a sub-fs speed figure-of-merit (FoM) by reducing the total capacitance (CTOT) and accomplishing a comparable output voltage droop (ΔVOUT) during a load transition. The proposed DLDO uses the segmented PMOS switches to fully turn on the NMOS array, which strengthens the intrinsic NMOS loop and maintains the undershoot and overshoot voltages of 88 and 42 mV, respectively, during an 88.4-mA load transition. In addition, with the aid of the proposed voltage doubler (VD)-based periodically refreshed level shifter (PRLS), the total capacitance of DLDO to drive NMOS array is reduced to 7.2 pF, which is 3.3× smaller than that of previous work, extending the input voltage (VIN) and load current (ILOAD) ranges up to 0.9 V and 140 mA, respectively. The proposed DLDO is fabricated using a 28-nm CMOS process and achieves a 0.12-fs speed FoM that is 42.5× smaller than the state-of-the-art designs." @default.
- W2989763669 created "2019-12-05" @default.
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- W2989763669 date "2019-01-01" @default.
- W2989763669 modified "2023-09-26" @default.
- W2989763669 title "A Sub-fs-FoM Digital LDO Using PMOS and NMOS Arrays With Fully Integrated 7.2-pF Total Capacitance" @default.
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- W2989763669 doi "https://doi.org/10.1109/jssc.2019.2952132" @default.
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