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- W2992120187 abstract "This paper presents a high-speed low-complexity two-bit level pipelined Viterbi decoder architecture for MB-OFDM UWB systems. As the add-compare-select unit (ACSU) is the main bottleneck of the Viterbi decoder, this paper proposes a novel two-bit level pipelined MSB-first ACSU, which is based on 2-step look-ahead techniques to reduce the critical path. The proposed ACSU architecture requires approximately 12% fewer gate counts and 9% faster speed than the conventional MSB-first ACSU. The proposed Viterbi decoder was implemented with CMOS standard cell technology and a supply voltage of 1.8V. It operates at a clock frequency of 870 MHZ and has a throughput of 1.74 Gb/s." @default.
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- W2992120187 date "2009-01-01" @default.
- W2992120187 modified "2023-09-24" @default.
- W2992120187 title "High-Speed Low-Complexity Two-Bit Level Pipelined Viterbi Decoder for UWB Systems" @default.
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