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- W2993719929 abstract "The design and simulation of a novel CMOS voltage mode parallel circuit is described. The circuit employs additional inhibitoy and local excitory feedback based on a common voltage computation and this improves both speed and precision drastically. As a result, a single stage cell provides better resolution and speed in comparison to previous works [1],[2]. where cascading is necessary in [1] to improve resolution. However in our previous work [3] we observed resolution is 0.5mv and the circuit was functioning only for two cells, and also low dynamic range. Whereas the circuit described here is tested with 3 (three) contending cells and was giving better dynamic range and resolution. Simulations in Cadence show that a single cell can resolve voltage differences as small as 0.2mV in around 60–80ns in comparison to 100mV in [1] and 0.5mV in [3]. Detailed simulation results along with appropriate mathematical relations have been provided. This circuit is a fundamental building block in the competitive layer of self organizing neural networks, non linear filters, fuzzy and neuromorphic systems." @default.
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- W2993719929 date "2010-01-22" @default.
- W2993719929 modified "2023-09-24" @default.
- W2993719929 title "A 200µv resolution and high speed VLSI Winner-take-all circuit for self-organising neural network" @default.
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