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• W2994104629 abstract "In this paper a novel digital data conversion scheme is proposed that may be applied in analog or digital data acquisition systems. In this scheme possible input redundancy of combinational logic circuit is eliminated by argument reduction. CAM (associative memory) is used in two implementations - for binary and ternary logic, respectively. For binary CAM hardware generators of column masks may be applied. The resulting digital structure can be easily implemented in FPGA." @default.
• W2994104629 created "2019-12-13" @default.
• W2994104629 creator A5075368295 @default.
• W2994104629 date "2019-09-01" @default.
• W2994104629 modified "2023-09-27" @default.
• W2994104629 title "Digital Data Convertion Using Content Addressable Memory" @default.
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• W2994104629 doi "https://doi.org/10.1109/idaacs.2019.8924304" @default.
• W2994104629 hasPublicationYear "2019" @default.
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