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- W2994793305 abstract "Abstract The increasing complexity of system on chips (SoCs) combined with a new generation of designs that combine multiple chips in a single package is creating new challenges in the design of packages, printed circuit boards (PCBs) and integrated circuits (ICs). The process typically involves three independent design processes – chip, package and PCB – carried out with point tools whose interface requires time-consuming manual processes that are error-prone and limit the potential for reuse. This challenge is being addressed by a new integrated 3D chip/package/board co-design environment that makes it possible to holistically optimize the package, board and IC design to a greater degree than was possible in the past by considering the system-level impact of each design decision. The new co-design approach enables designers to optimize routability via pin assignment and I/O placement to achieve minimum layer counts between chip, package and board. The end result is higher performance." @default.
- W2994793305 created "2019-12-26" @default.
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- W2994793305 date "2019-10-01" @default.
- W2994793305 modified "2023-09-25" @default.
- W2994793305 title "System I/O Optimization with SoC, SiP, PCB Co-Design" @default.
- W2994793305 doi "https://doi.org/10.4071/2380-4505-2019.1.000013" @default.
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