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- W2998989983 abstract "Prior studies have shown that the retention time of the non-volatile spin-transfer torque RAM (STT-RAM) can be relaxed in order to reduce STT-RAM’s write energy and latency. However, since different applications may require different retention times, STT-RAM retention times must be critically explored to satisfy various applications’ needs. This process can be challenging due to exploration overhead, and exacerbated by the fact that STT-RAM caches are emerging and are not readily available for design time exploration. This paper explores using known and easily obtainable statistics (e.g., SRAM statistics) to predict the appropriate STT-RAM retention times, in order to minimize exploration overhead. We propose an STT-RAM Cache Retention Time (SCART) model, which utilizes machine learning to enable design time or runtime prediction of right-provisioned STT-RAM retention times for latency or energy optimization. Experimental results show that, on average, SCART can reduce the latency and energy by 20.34% and 29.12%, respectively, compared to a homogeneous retention time while reducing the exploration overheads by 52.58% compared to prior work." @default.
- W2998989983 created "2020-01-23" @default.
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- W2998989983 date "2019-10-01" @default.
- W2998989983 modified "2023-09-25" @default.
- W2998989983 title "SCART: Predicting STT-RAM Cache Retention Times Using Machine Learning" @default.
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- W2998989983 doi "https://doi.org/10.1109/igsc48788.2019.8957182" @default.
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