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- W3003876475 abstract "A comprehensive SRAM test must guarantee the correct functioning of each cell of the memory (ability to store and to maintain data), and the corresponding addressing, write and read operations. SRAM testing is mainly based on the concept of fault model used to mimic faulty behaviors. Traditionally, the effects of bit line coupling capacitances have not been considered during the fault analysis. However, recent works show the increasing impact of bit line coupling capacitances on the SRAM behavior. This paper reviews and discusses preview works addressing the issues coming from bit line parasitic capacitances and data contents on SRAM testing, pointing out the impacts of these effects on the existing test solutions. Then, we introduce two optimizations of the state-of-the-art test solution able to take into account the influence of bit line coupling capacitances while reducing the test length of about 60% and 80%, respectively." @default.
- W3003876475 created "2020-02-07" @default.
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- W3003876475 date "2012-03-15" @default.
- W3003876475 modified "2023-09-24" @default.
- W3003876475 title "Optimized March Test Flow for Detecting Memory Faults in SRAM Devices Under Bit Line Coupling" @default.
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