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W3005785620 abstract "We report for the first time reliable 2 ns switching of spin-transfer torque magneto-resistive random access memory (STT-MRAM) devices by demonstrating 100% write-error-rate (WER) yield at 1e-6 write-error floor of 254 devices with tight distributions and steep WER slope at a nominal size of 49 nm. A single device was demonstrated with 2 ns write pulses to have less than 1e-11 write-error rate, limited only by test time. We further demonstrate reliable 3 ns switching performance, with 99% WER yield at 1e-6 write-error floor of 256 devices with nominal size of 43 nm and a single device with less than 1e-11 write-error rate with a completely different free layer materials design. These two different free layer materials designs address one of the major remaining challenges for STT-MRAM to replace SRAM for last level cache (LLC) applications." @default.
W3005785620 created "2020-02-24" @default.
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W3005785620 date "2019-12-01" @default.
W3005785620 modified "2023-10-01" @default.
W3005785620 title "Spin-transfer torque MRAM with reliable 2 ns writing for last level cache applications" @default.
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W3005785620 doi "https://doi.org/10.1109/iedm19573.2019.8993604" @default.
W3005785620 hasPublicationYear "2019" @default.
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