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- W3009804865 abstract "Fast Fourier transform (FFT) is an essential algorithm in digital signal processing and advanced mobile communications. With the continuous development of modern technology, the area-power efficient hardware implementation of FFT has attracted a lot of attention. In this article, a novel design for FFT implementation is proposed. The number of resource-expensive multiplications in our design is decreased by a twiddle factor merging technique that reduces the hardware area. Subsequently, a common subexpression sharing scheme is applied to reuse the hardware resources to further save the hardware area. In addition, a magnitude-response aware approximation algorithm is proposed for applications where the transformation accuracy can be compromised a little bit for lesser hardware area and power dissipation. Logic synthesis shows that the proposed 16-point FFT architecture can save hardware area and power dissipation on application-specific integrated circuit (ASIC) by up to 65.7% and 53.1% compared with recently published designs. Similarly, the proposed 32-point FFT architecture achieves up to 58.8% reduction on hardware area and 60.0% reduction on power dissipation on ASIC." @default.
- W3009804865 created "2020-03-13" @default.
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- W3009804865 date "2020-12-01" @default.
- W3009804865 modified "2023-10-17" @default.
- W3009804865 title "A Novel Area-Power Efficient Design for Approximated Small-Point FFT Architecture" @default.
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- W3009804865 doi "https://doi.org/10.1109/tcad.2020.2978839" @default.
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