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- W3011867112 abstract "In this article, a new architecture of bit-serial polynomial basis (PB) multipliers over the binary extension field $GF(2^m)$ G F ( 2 m ) generated by irreducible trinomials is presented. Bit-serial $GF(2^m)$ G F ( 2 m ) PB multiplication offers a performance/area trade-off that is very useful in resource constrained applications. The architecture here proposed is based on LFSR ( Linear-Feedback Shift Register ) and can perform a multiplication in $m$ m clock cycles with a constant propagation delay of $T_{A} + T_{X}$ T A + T X . These values match the best time results found in the literature for bit-serial PB multipliers with a slight reduction of the space complexity. Furthermore, the proposed architecture can perform the multiplication of two operands for $t$ t different finite fields $GF(2^m)$ G F ( 2 m ) generated by $t$ t irreducible trinomials simultaneously in $m$ m clock cycles with the inclusion of $t(m-1)$ t ( m - 1 ) flipflops and $tm$ t m XOR gates." @default.
- W3011867112 created "2020-03-23" @default.
- W3011867112 creator A5041677215 @default.
- W3011867112 date "2020-01-01" @default.
- W3011867112 modified "2023-10-14" @default.
- W3011867112 title "LFSR-based Bit-Serial $GF(2^m)$ Multipliers using Irreducible Trinomials" @default.
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- W3011867112 doi "https://doi.org/10.1109/tc.2020.2980259" @default.
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