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• W3012298678 abstract "This paper presents the VLSI implementation of a Bit serial multiplier for multiplication in binary Finite Field GF(2m) and is based on Shift and Add algorithm. The polynomial base representation is used. The multiplier generates the result by shifting one of the multiplicand. Form bit inputs; it produces output after m−1 clock cycles. The value of m can vary up to 283 bits. Multiplier is designed using Verilog HDL. The designed Multiplier is simulated using NG Spice. The proposed design is synthesized in CADENCE Encounter. Using the low power VLSI methodology power consumption is reduced. Proposed multiplier is implemented using CADENCE virtuoso tool set using GPDK45nm technology." @default.
• W3012298678 created "2020-03-23" @default.
• W3012298678 creator A5053404718 @default.
• W3012298678 creator A5058145709 @default.
• W3012298678 date "2019-03-01" @default.
• W3012298678 modified "2023-10-03" @default.
• W3012298678 title "Design of Power Efficient Bit Serial Finite Field GF(2m) Multiplier" @default.
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• W3012298678 doi "https://doi.org/10.1109/i2ct45611.2019.9033682" @default.
• W3012298678 hasPublicationYear "2019" @default.
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