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- W3015599372 abstract "FPGA-based implementation of tree-based classifiers has been a very promising approach due to the ability of FPGA to execute tasks in parallel, which speeds up the processing tasks and saves power. The challenge with FPGA implementation is the need to build all classifier components in hardware, structure format, which is time-consuming and does not follow the best practices in creating modular design architecture. This paper addresses this issue by proposing a hardware-software codesign implementation of a tree-based classifier that uses ID3 algorithm for classification tasks. We used the Xilinx microblaze processor inside the FPGA to execute ID3 algorithm functions, while using hardware modules for pre-processing and feature engineering tasks." @default.
- W3015599372 created "2020-04-17" @default.
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- W3015599372 date "2019-11-01" @default.
- W3015599372 modified "2023-09-30" @default.
- W3015599372 title "FPGA-based Implementation of a Tree-based Classifier using HW-SW Co-design" @default.
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- W3015599372 doi "https://doi.org/10.1109/accs-peit48329.2019.9062867" @default.
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