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- W3015890672 abstract "In this paper, we propose a novel CGRA architecture and associated compilation flow supporting both integer and floating-point computations for energy efficient acceleration of DSP applications. Experimental results show that the proposed accelerator achieves a maximum of 4.61 × speedup compared to a DSP optimized, ultra low power RISC-V based CPU while executing seizure detection, a representative of wide range of EEG signal processing applications with an area overhead of 1.9×. The proposed CGRA achieves a maximum of 6.5× energy efficiency compared to the CPU." @default.
- W3015890672 created "2020-04-17" @default.
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- W3015890672 date "2020-05-01" @default.
- W3015890672 modified "2023-09-24" @default.
- W3015890672 title "Energy Efficient Acceleration Of Floating Point Applications Onto CGRA" @default.
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- W3015890672 doi "https://doi.org/10.1109/icassp40776.2020.9054613" @default.
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