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- W3016138070 abstract "A 4-GHz sub-harmonically injection-locked phase locked loop (ILPLL) with on-chip calibration is presented. The injection timing and pulsewidth of the injected pulse are self-calibrated to achieve a low phase noise. The phase noise of the proposed ILPLL was -110.1 dBc/Hz at 1-MHz offset frequency, while that of the conventional PLL was -104.8 dBc/Hz. The measured reference spur was also reduced from -44.36 dBc to -52.87 dBc with the proposed calibration technique. Fabricated in a 28-nm CMOS process, the proposed ILPLL occupies 0.09 mm2. Operating at 4 GHz, it consumes 11.4 mW from a 1.0-V power supply." @default.
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- W3016138070 date "2019-11-01" @default.
- W3016138070 modified "2023-09-27" @default.
- W3016138070 title "A 4-GHz Sub-harmonically Injection-Locked Phase-Locked Loop with Self-Calibrated Injection Timing and Pulsewidth" @default.
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- W3016138070 doi "https://doi.org/10.1109/a-sscc47793.2019.9056966" @default.
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