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- W3021941610 abstract "Training DNN is a time-consuming process and requires intensive memory resources. Many software-based approaches were proposed to improve the performance and energy efficiency of inferring DNNs. Meanwhile training hardware is still received limited attention. In this work, we present a novel DRAM architecture with critical-bit protection. Our method targets main memory and graphical memory of the training system. Experimented on GEM5-GPGPUsim, our proposed DRAM architecture can achieve 23% and 12% DRAM energy reduction with floating point 32bit on main and graphical memories, respectively. Also, it further improves system's performance by 0.43˜ 4.12% while maintaining a negligible accuracy drops in training DNNs." @default.
- W3021941610 created "2020-05-13" @default.
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- W3021941610 creator A5045028723 @default.
- W3021941610 date "2019-10-06" @default.
- W3021941610 modified "2023-09-23" @default.
- W3021941610 title "Energy-efficient DNN-training with Stretchable DRAM Refresh Controller and Critical-bit Protection" @default.
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- W3021941610 doi "https://doi.org/10.1109/isocc47750.2019.9078532" @default.
- W3021941610 hasPublicationYear "2019" @default.
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