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- W3022978916 abstract "A usually consists of a voltage controlled oscillator (VCO) locked to a reference clock Ref by a feedback loop with: a phase detector (PD), a charge pump (CP), a loop filter (LF) and a frequency divider with ratio N (÷N). Every component will add noise and power to the PLL. In an ideal case, the jitter and power should be mostly determined by the VCO and Ref, while the other components like PD, CP, LF and divider adds negligible noise and consumes negligible power. This paper describes this PLL Utopia and discusses how it can be achieved through architecture and circuit design innovations." @default.
- W3022978916 created "2020-05-13" @default.
- W3022978916 creator A5049999335 @default.
- W3022978916 date "2019-10-06" @default.
- W3022978916 modified "2023-09-23" @default.
- W3022978916 title "Low Jitter and Low Power PLL：Towards The Utopia" @default.
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- W3022978916 doi "https://doi.org/10.1109/isocc47750.2019.9078535" @default.
- W3022978916 hasPublicationYear "2019" @default.
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