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- W3023462124 abstract "In this work we present the first complete design, silicon implementation and measurements in 22 nm FD-SOI of the Network Training Accelerator (NTX) architectural concept [1]. NTX is based on a newly designed partial carrysave wide-inside (300 bit) fused multiply-accumulate (FMAC) unit ensuring IEEE 754 compliance and a Root Mean Squared Error 1.7_lower than a conventional 32 bit FPU on long accumulations such as dot products and convolutions." @default.
- W3023462124 created "2020-05-13" @default.
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- W3023462124 date "2019-10-06" @default.
- W3023462124 modified "2023-10-14" @default.
- W3023462124 title "NTX: A 260 Gflop/sW Streaming Accelerator for Oblivious Floating-Point Algorithms in 22 nm FD-SOI" @default.
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- W3023462124 doi "https://doi.org/10.1109/isocc47750.2019.9078495" @default.
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