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- W3023876827 abstract "Several interesting topologies emerge by incorporating the third dimension in the design of networks-on-chip (NoC). An analytic model for the zero-load latency of each network that considers the effect of the topology on the performance of a 3-D NoC is developed. A tradeoff between the number of nodes utilized in the third dimension of the network, which reduces the average number of hops traversed by a packet, and the number of physical planes used to integrate the processing elements (PE) of the network, which decreases the wire delay of the communication channel, is evaluated. A performance improvement of up to 33% is demonstrated for 3-D NoC as compared to a traditional 2-D NoC topology for a network size of N= 128 nodes." @default.
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- W3023876827 date "2006-09-01" @default.
- W3023876827 modified "2023-09-27" @default.
- W3023876827 title "3-D Topologies for Networks-on-Chip" @default.
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- W3023876827 doi "https://doi.org/10.1109/socc.2006.283899" @default.
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