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• W3025863817 endingPage "1293" @default.
• W3025863817 startingPage "1293" @default.
• W3025863817 abstract "In recent technology nodes, interconnect scaling has become a major bottleneck for the reduction of the area of CMOS circuits. In the near future, interconnect dimensions will reach 10 nm and below. Reducing the cross-sectional area of interconnect wires and vias increases their resistance and consequently degrades the performance of the circuit. This geometrical effect is aggravated by an increased resistivity of the conductor metal, Cu, due to enhanced surface and grain boundary scattering. Moreover, it becomes increasingly difficult to ensure the reliability of scaled Cu interconnects. Barrier layers, such as TaN, are required to limit diffusion into the surrounding dielectrics. Resistance to electromigration is reduced in small dimensions, which can be mitigated e.g. by Co liners. However, both barriers and liners reduce the volume available for Cu while contributing little to the line conductance." @default.
• W3025863817 created "2020-05-21" @default.
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• W3025863817 date "2020-05-01" @default.
• W3025863817 modified "2023-10-18" @default.
• W3025863817 title "(Invited) Alternative Metals for Beyond-Cu Interconnects" @default.
• W3025863817 doi "https://doi.org/10.1149/ma2020-01221293mtgabs" @default.
• W3025863817 hasPublicationYear "2020" @default.
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