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- W3032957346 abstract "Classic IC technology scalingScaling laws show that transistor performance and dynamic energy consumption improve with reduced dimensions and scalingScaling voltages. Ideal scaling is called constant electric field scaling or Dennard scaling [1]. Thus, for a few decades, technology evolution has brought “more for less”. For a given functionality less area and less energy per operation was required with each new technology generation. This led us to the smartphone, GPS, (almost) self-driving car, Internet of Things, era we live today. However, advanced scaling puts an end to the fairy tale: increased leakage and increased technological variability complicates the “more for less” paradigm. Today, and in the foreseeable future, we must deal with the energy performance trade off in a much more active and deliberate way. For digital design, this means that for physical design the circuit level is back from never fully gone. Careful library design, optimal choice of supply voltages, plural and advanced architectural techniques to deal with timing variability impose themselves. In this chapter an overview of this scenery is given." @default.
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- W3032957346 date "2020-01-01" @default.
- W3032957346 modified "2023-09-26" @default.
- W3032957346 title "Dealing with the Energy Versus Performance Tradeoff in Future CMOS Digital Circuit Design" @default.
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- W3032957346 doi "https://doi.org/10.1007/978-3-030-18338-7_7" @default.
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