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- W3033343183 abstract "Abstract High density, low power consumption, and low cost memory cells are exceedingly desired due to the continuous scaling of the memory cells and the augmentation in memory array dimensions. The program/erase (P/E) speed of the floating-gate memory can be enhanced by reducing the thickness of the tunnel oxide to sub 2.5 nm, which would result in 100 ns P/E time at a tolerable programming voltage ( 10 years). In this chapter, we study the effect of embedding 2-nm Si nanoparticles in the charge trapping layer on the memory device behavior. Two memory structures are studied with a ZnO channel and different charge trapping layers: Si nanoparticles only and Si nanoparticles embedded in a ZnO layer." @default.
- W3033343183 created "2020-06-12" @default.
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- W3033343183 date "2020-01-01" @default.
- W3033343183 modified "2023-09-25" @default.
- W3033343183 title "Laser ablated nanoparticles synthesis" @default.
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- W3033343183 doi "https://doi.org/10.1016/b978-0-12-822342-0.00005-5" @default.
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