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- W3036016985 abstract "The purpose of this paper is to present the performance of 8-bit pipelined analog-to-digital converter (ADC) with the implementation of gain-enhancement technique towards the conventional operational amplifier (op-amp). The gain-enhancement technique is the employment of a pair of NMOS devices to isolate the differential input devices of the opamp from the cascode devices. Thus, the open-loop DC gain can be further enhanced without deteriorating the unity-gain bandwidth of the op-amp. The effect of the employment of the NMOS devices is analysed and implemented in the op-amp that acts as the main component in developing this 8-bit pipelined ADC. The fabrication used Silterra 180 nm CMOS process. The silicon area by the ADC is 1.44 mm <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</sup> . Measured results show that the DNL error, SNR and SFDR are within −1 to +0.5 LSB, 27 dB and 46.38 dB, respectively at the input frequency of 2 MHz and sampling rate of 8 MS/s. The static power consumption is 27 mW with a supply voltage of 1.8 V." @default.
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- W3036016985 date "2020-04-01" @default.
- W3036016985 modified "2023-09-29" @default.
- W3036016985 title "A 1.8 V 8-Bit Pipelined ADC With Integrated Folded Cascode Op-Amp in CMOS 180 nm" @default.
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- W3036016985 doi "https://doi.org/10.1109/edtm47692.2020.9117901" @default.
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