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- W3036495116 abstract "In this work, device-level to circuit-level assessment for a vertical Ge/Si heterojunction vertical tunnel field effect transistor (TFET) with and without gate-drain underlap structure has been reported. A source pocket is considered in between source and channel for both the structure to enhance the performance of the device. The effect of gate-drain underlap on gate to drain parasitic capacitance <tex xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>$(mathrm{C}_{mathrm{gd}})$</tex> is analyzed. The performance in terms of <tex xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>$mathbf{I}_{mathrm{ON}}/mathbf{I}_{mathrm{OFF}}$</tex> and SS are investigated for the proposed devices. Gate-drain underlapped Ge/Si heterojunction vertical TFET is used to achieve better cut-off frequency and maximum frequency at <tex xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>$mathbf{V}_{mathrm{DS}}=0.5 mathrm{V}$</tex> which is essential for RF applications. The DC and transient response of a digital inverter circuit based on proposed devices have been analyzed using Verilog-A model in the CADENCE tool." @default.
- W3036495116 created "2020-06-25" @default.
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- W3036495116 date "2020-04-01" @default.
- W3036495116 modified "2023-09-27" @default.
- W3036495116 title "Performance Comparison of Ge/Si Hetero-Junction Vertical Tunnel FET with and Without Gate-Drain Underlapped Structure with Application to Digital Inverter" @default.
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- W3036495116 doi "https://doi.org/10.1109/edtm47692.2020.9117840" @default.
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