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- W3036561617 abstract "Networks-on-chip (NoCs) are playing a critical role in modern multicore architecture, and NoC security has become a major concern. Maliciously implanted hardware Trojans (HTs) inject faults into on-chip communications that saturate the network, resulting in the leakage of sensitive data via side channels and significant performance degradation. While existing techniques protect NoCs by detecting and isolating HT-infected components, they inevitably incur occasional inaccurate detection with considerable network latency and power overheads. We propose TSA-NoC, a learning-based design framework for secure and efficient on-chip communication. The proposed TSA-NoC uses an artificial neural network for runtime HT-detection with higher accuracy. Furthermore, we propose a deep-reinforcement-learning-based adaptive routing design for HT mitigation with the aim of minimizing network latency and maximizing energy efficiency. Simulation results show that TSA-NoC achieves up to 97% HT-detection accuracy, 70% improved energy efficiency, and 29% reduced network latency as compared to state-of-the-art HT-mitigation techniques." @default.
- W3036561617 created "2020-06-25" @default.
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- W3036561617 date "2020-09-01" @default.
- W3036561617 modified "2023-10-08" @default.
- W3036561617 title "TSA-NoC: Learning-Based <u>T</u>hreat Detection and Mitigation for <u>S</u>ecure Network-on-Chip <u>A</u>rchitecture" @default.
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- W3036561617 doi "https://doi.org/10.1109/mm.2020.3003576" @default.
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