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- W3040878082 abstract "This paper presents a fast method to extract logic functions of look-up tables (LUTs) from a bitstream in Xilinx FPGAs. In general, FPGAs utilize LUTs as a primary resource to realize a logic function, and a typical N-input LUT comprises 2N 1-bit SRAM and N – 1 multiplexers. Whereas the previous research demands 2N exhaustive processing to find a mapping rule between an LUT and a bitstream, the proposed method decreases the processing to 2N by eliminating unnecessary processing. Experimental results show that the proposed method can reduce reversing time by more than 57% and 85% for Xilinx Spartan-3 and Virtex-5 compared to the previous exhaustive algorithm. It is noticeable that the reduction time becomes more significant as a commercial Xilinx FPGA tends to include a more tremendous number of LUTs." @default.
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- W3040878082 date "2020-07-11" @default.
- W3040878082 modified "2023-09-25" @default.
- W3040878082 title "Fast Logic Function Extraction of LUT from Bitstream in Xilinx FPGA" @default.
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- W3040878082 doi "https://doi.org/10.3390/electronics9071132" @default.
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