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• W3042679116 startingPage "106669" @default.
• W3042679116 abstract "Enhancing the competitive advantages of wafer fabs is crucial to increase the number of gross dies per wafer and to reduce average die cost. Most of existing studies about IC (integrated circuit) feature design focus on yield enhancement, yet little research has been done on cost reduction through increasing gross die number and decreasing shot number simultaneously. To generate the alternative feature design to improve wafer exposure effectiveness, a prediction model between chip size and gross die number and shot number was built through amount of data collection and model training. However, it’s difficult to consider different exposure conditions under various parameter setting of amount of IC features. In order to fill the gap of considering real setting, this study aims to propose a two-phase non-dominated sorting particle swarm optimization (TNSPSO) method to maximize number of gross die and minimize the shot number and then suggests alternative chip features for IC designers. First, non-dominated sorting algorithm is used to find the solutions on the frontier. Second, these particles on the frontier are diffused toward the sparse region on the frontier. To evaluate the validity of proposed approach, two conventional heuristic algorithms, non-dominated sorting genetic algorithm II (NSGA-II) and multi-objective particle swarm optimization (MOPSO) were selected . The experiment results showed that the proposed method not only capture the solutions closer to the Pareto frontier but also has better convergence and diversity of the solutions than the other methods. The proposed approach can assist IC designer in effectively deriving chip layout design with enhancement of wafer exposure effectiveness." @default.
• W3042679116 created "2020-07-23" @default.
• W3042679116 creator A5047554774 @default.
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• W3042679116 date "2020-09-01" @default.
• W3042679116 modified "2023-10-10" @default.
• W3042679116 title "A two-phase non-dominated sorting particle swarm optimization for chip feature design to improve wafer exposure effectiveness" @default.
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• W3042679116 doi "https://doi.org/10.1016/j.cie.2020.106669" @default.
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