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- W3048762142 abstract "This paper presents a Fractional-N (Frac-N) digital phase-locked loop (DPLL) that resolves phase error (PE) in fully differential voltage (FDV) domain, where power-efficient PE detection can be accomplished with higher CMRR, lower PVT sensitivity, finer resolution and better linearity as compared to gate delay-dependent time domain. The implemented DPLL covers the frac-N operation by a 10b DAC in voltage domain (V-domain). A differential dv/dt ramp is employed to linearly transfer the frac-N phase difference into a small range voltage error, which is digitized by a narrow range but fine resolution 7b ADC. The DPLL achieves an integrated RMS jitter of 101fs with −56dBc worst-case fractional spur and consumes 9.2mW which translates to a FoM of −250.3dB." @default.
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- W3048762142 date "2020-06-01" @default.
- W3048762142 modified "2023-09-23" @default.
- W3048762142 title "A 3.3-GHz 101fsrms-Jitter, −250.3dB FOM Fractional-N DPLL with Phase Error Detection Accomplished in Fully Differential Voltage Domain" @default.
- W3048762142 doi "https://doi.org/10.1109/vlsicircuits18222.2020.9162777" @default.
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