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- W3048950007 abstract "Logical effort is the ratio of the input capacitance of a gate to the input capacitance of an inverter delivering the same output current.. Conventional methods use repetitive manual testing guided by Logical Effort (LE).In our work, we choose gate widths inside the circuit as parameters to be optimized in order to achieve the target delay, using LE.The main objective of the paper is to calculate the delay using VerilogHDL and synthesized the output driven by it by increasing the speed using optimized paths." @default.
- W3048950007 created "2020-08-18" @default.
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- W3048950007 date "2014-01-01" @default.
- W3048950007 modified "2023-10-02" @default.
- W3048950007 title "DESIGN OF ALU-64BIT FOR HIGH SPEED USING LOGICAL EFFORT" @default.
- W3048950007 cites W2058254562 @default.
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- W3048950007 doi "https://doi.org/10.47893/ijess.2014.1163" @default.
- W3048950007 hasPublicationYear "2014" @default.
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